In the field of semiconductor manufacturing, as CMOS technology continues to scale down the size to nanometers, many challenges start emerging. One of the challenges on scaling down the size is process variations. These variations affect the transistor characteristics, which in terms produce critical path to logic circuits to have different delays, memory read/write failure, and higher static currents. In general, circuits need to be designed conservatively to cope with performance losses introduced by process variations. That is, the manufacturer needs to reserve more margins which lead to larger area (cost) and higher power consumption.
Therefore, there is a need to understand and quantify process-induced variability.